Profiel

• You are a dynamic and highly motivated engineer with at least four years of experience in digital IC design
• You have experience with front-end ASIC or FPGA design in VHDL and/or Verilog and/or SystemVerilog
• You have experience with front-end verification, preferably in SystemVerilog + UVM, to write directed tests, constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverage
• You have experience with digital synthesis, logic equivalence checking (LEC) and Static Timing Analysis (STA)
• Experience with UPF and/or CPF and DFT and ATPG is a plus
• Experience with scripting and programming languages such as Python and C is a plus
• Experience with any of the following protocols and techniques is a plus: SPI, I2C, UART, CAN, LIN, SENT, DSP, CRC, FSM design, MCU
• You are a self-motivated, efficient professional able to work alone or in teams
• You offer quality and reliability to colleagues, customers and management, willing to share knowledge and able to communicate efficiently
• You are fluent in English, both written and spoken